The present invention relates to a data line drive circuit for a panel display, and more specifically to a panel display data line drive circuit capable of driving, with a low power consumption, a panel display typified by a liquid crystal display such as a TFT-LCD (thin film transistor driven liquid crystal display) and an active matrix drive type organic EL display.
At present, liquid crystal displays are widely used in various fields. When the liquid crystal display is incorporated into a portable instrument, it is demanded to make a power consumption of the portable instrument as small as possible, in order to allow to unintermittently utilize the portable instrument with no necessity of an electric charging. As one means for achieving this demand, a power consumption of the liquid crystal display is required to be reduced to a minimum. For this purpose, various power saving approaches have been proposed, and some of them has been reduced into practice.
A liquid crystal display incorporated in a hand-held type portable instrument such as a PDA, a portable game instrument and a portable telephone has a relatively small display screen size and correspondingly a small number of pixels. In the case of driving a small-size TFT-LCD panel having a relatively small number of pixels, a horizontal scan frequency is low and a load capacitance of the TFT-LCD panel is also small. Therefore, in a power consumption of a data line driving circuit for the liquid crystal display, a static consumed electric power of an output buffer takes a large proportion.
In brief, the power consumption of the data line driving circuit for the TFT-LCD panel is divided into an electric power for charging a data line in the TFT-LCD panel, and an electric power consumed by the data line driving circuit itself. In the case of the small-size TFT-LCD panel having a relatively small number of pixels, since a load capacitance of the data line is small, the electric power for charging the data line is correspondingly small. As a result, the proportion of the electric power consumed by the data line driving circuit itself to a whole power consumption of the data line driving circuit for the TFT-LCD panel, is large. In addition, the proportion of the static consumed electric power of the output buffer to the electric power consumed by the data line driving circuit itself is large. A similar problem occurs in a data line driving circuit configured to drive a data line in accordance with a gray-scale voltage in a small display panel such as an active matrix drive type organic EL display, other than the liquid crystal display.
Here, examining a prior art data line driving circuit for a liquid crystal display, JP-A-07-013528 and JP-A-07-104703 propose to drive the LCD panel in a time division manner. However, this structure is intended to reduce the number of external interconnections between the LCD panel and a column driver circuit discrete therefrom.
Furthermore, the data line driving circuits of these patent publications are constructed to simultaneously and once precharge all data lines to a fixed voltage corresponding to for example a high level, before each data line is driven to a designated drive voltage, and thereafter to discharge each precharged data line to the designated drive voltage. This is based on a recognition that a discharging time of the data line is shorter than a charging time of the data line. This procedure can make it possible to shorten a time required for driving the data line to the designated drive voltage. However, since all the data lines are simultaneously precharged to the fixed voltage corresponding to for example the high level regardless of the designated drive voltage, when the designated drive voltage is near to a low level, there is possibility that the time required for driving to the designated drive voltage is rather longer than the case of driving to the designated drive voltage with no precharging.
Alternatively, JP-A-07-173506 proposes to supply an output of a digital-to-analog converter to the data line in a time division manner. However, this structure is intended to prevent the scale-up of the whole data line drive circuit occurring with increase in the number of pixels, and to reduce the power consumption.
Furthermore, JP-A-07-173506 proposes, as a second invention, to precharge the data lines to a maximum drive voltage when the drive output voltage is not smaller than an intermediate drive voltage, and to a minimum drive voltage when the drive output voltage is not larger than an intermediate drive voltage. However, it does not disclose a specific method for selecting the precharge voltage.
In addition, JP-A-11-119741 proposes to precharge one of adjacent data lines to a maximum drive voltage, and then, to drive the precharged data line to a designated drive voltage by use of an operational amplifier having a high current drawing capacity, and further, to precharge the other of the adjacent data lines to a minimum drive voltage, and then, to drive the precharged data line to a designated drive voltage by use of an operational amplifier having a high current supplying capacity, so that a voltage variation between opposing electrodes can be suppressed, and a display unevenness is reduced. According to this disclosed invention, each data line is ceaselessly precharged to either one fixed voltage of the maximum drive voltage and the minimum drive voltage, regardless of a designated drive voltage to be applied to the data line concerned.
None of the above mentioned prior art examples is intended to reduce the static consumed electric power in the output buffer in the data line drive circuit for the liquid crystal display. Accordingly, heretofore, there is no data line drive circuit for the liquid crystal display, which reduces the power consumption of the liquid crystal display, by reducing the static consumed electric power in the output buffer in the data line drive circuit for the liquid crystal display.
Accordingly, it is an object of the present invention to provide a data line drive circuit for a panel display, capable of driving the panel display with a reduced power consumption, by reducing the static consumed electric power in the output buffer in the data line drive circuit for the panel display such as a liquid crystal display.
According to a first aspect of the present invention, there is provided a data line drive circuit for a panel display, comprising a selection means receiving a plurality of voltages corresponding to each plurality of data lines, of a number of data lines of the panel display, analog buffers each provided in common for a plurality of data lines, for receiving and outputting the voltage alternatively selected by the selection means, a distribution means receiving an output of each analog buffer for selectively distributing the output of the analog buffer to a selected one of the plurality of data lines, a precharge means provided for each of the plurality of data lines, for precharging a corresponding data line to either a high drive voltage or a low drive voltage, in accordance with at least the most significant bit signal of a digital data corresponding to the corresponding data line, and a control means for controlling the selection means, the distribution means and the precharge means, wherein each scan line selection period includes a precharge period and a plurality of writing periods succeeding to the precharge period, and during the precharge period, the control means controls the distribution means to separate the output of the analog buffers from all the data lines, and activates each precharge means to precharge all the data lines, and during the plurality of writing periods, the control means inactivates each precharge means and controls the selection means and the distribution means in such a manner that during a first writing period of the plurality of writing periods, the voltage corresponding to a first data line of the plurality of data lines is supplied to the analog buffer and the output of the analog buffer is supplied to the first data line, and during a second writing period of the plurality of writing periods, the voltage corresponding to a second data line of the plurality of data lines is supplied to the analog buffer and the output of the analog buffer is supplied to the second data line.
According to a second aspect of the present invention, there is provided a data line drive circuit for a panel display in which a digital data of one scan line is divided into P blocks, where P is an integer larger than 1, and similarly, a number of data lines are divided into P blocks, the data line drive circuit comprising a first data latch for latching at least the most significant bit signal of the digital data of one block of the P blocks, in units of a block, a second data latch for latching the digital data of one block of the P blocks, in units of a block, a D/A converter receiving the digital data outputted from the second data latch for generating a corresponding analog gray-scale voltage, analog buffers each provided in common to P data lines, for receiving the analog gray-scale voltage outputted from the D/A converter to output the analog gray-scale voltage, a distribution means receiving an output of the analog buffer to alternatively distribute the output of the analog buffer to a selected one of the P data lines, a precharge means provided for each of the number of data lines, for precharging the corresponding data line to either a high drive voltage or a low drive voltage in accordance with at least the most significant bit signal of the digital data corresponding to the corresponding data line, and a control means for controlling the first and second data latches, the distribution means and the precharge means, wherein during a first period of each scan line selection period, the control means controls the precharge means to precharge each of the data lines in a first block to either a high drive voltage or a low drive voltage in accordance with at least the most significant bit signal of the digital data of the first block, latched in the first data latch, and during a second period of each scan line selection period, the control means controls the distribution means to supply the data lines in the first block with a voltage which is obtained by D/A converting the digital data of the first block held in the second data latch by action of the D/A converter and supplying the output of the D/A converter through the analog buffer, and also the control means controls the precharge means to precharge each of the data lines in a second block to either a high drive voltage or a low drive voltage in accordance with at least the most significant bit signal of the digital data of the second block, latched in the first data latch, and further, during a third period of each scan line selection period, the control means controls the distribution means to supply the data lines in the second block with a voltage which is obtained by D/A converting the digital data of the second block held in the second data latch by action of the D/A converter and supplying the output of the D/A converter through the analog buffer.
In the P blocks of the digital data of one scan line, a first block consists of one item of digital data for every P items of digital data counted from a first item of digital data in the digital data of one scan line, and a second block consists of one item of digital data for every P items of digital data counted from a second item of digital data in the digital data of one scan line. In this case, in the P blocks of data lines in the number of data lines, a first block consists of one data line for every P data lines counted from a first data line in the number of data lines, and a second block consists of one data line for every P data lines counted from a second data line in the number of data lines. However, the manner of allocating the digital data and the data lines into the P blocks, is in now way limited to the above mentioned manner, but it would be apparent to persons skilled in the art that various manner could be considered.
According to the present invention, it is no longer necessary to provide one analog buffer for each data line of a number of data lines in the panel display. Therefore, if one analog buffer is provided for each two data lines, the number of analog buffers can be halved. If one analog buffer is provided for each three data lines, the number of analog buffers can be reduced to one third. Furthermore, if one analog buffer is provided for each P data lines, the number of analog buffers can be reduced to 1/P.
The analog buffer ordinarily needs a steady idling current (static consumed electric current) for maintaining the operation. Therefore, since the number of analog buffers is reduced, the power consumption can be reduced by the total static consumed electric current of the omitted analog buffers, and further, the required area can be correspondingly reduced.
In addition, if the analog buffer is constituted of the data line drive circuit disclosed by the inventor of this application in Japanese Patent application No. Heisei 11-145768, a high speed operation is possible even if the idling current of the analog buffer itself is reduced. Accordingly, it is possible to realize the analog buffer having a further reduced power consumption.
Furthermore, if the precharging is carried out without exception before the gray-scale voltage is outputted, the analog buffer must carry out the precharging and the outputting of the gray-scale voltage in each one scan line selection period. If this operation is carried out in a time division manner for a plurality of data lines, it becomes necessary to carry out the precharging a plurality of times. In the present invention, however, the precharging and the outputting of the gray-scale voltage are made independent of each other, and the precharging required for a plurality of data lines is carried out simultaneously, and only the outputting of the gray-scale voltage is carried out in a time division manner. Alternatively, both the precharging and the outputting of the gray-scale voltage are carried out in a time division manner, but only the precharging for the data lines of the first block is carried out independently, the precharging for the data lines of the second and succeeding blocks is carried out in parallel at the same time as the outputting of the gray-scale voltage to the data lines of a just preceding block is carried out. Thus, not only the precharge period but also the gray-scale voltage outputting periods can be elongated in comparison with the case that one data line driving composed of the precharging and the outputting of the gray-scale voltage is carried out in a simple time division manner.
In addition, the precharge voltage of each data line is determined by a polarity signal and the most significant bit signal of the digital data indicating an output gray-scale voltage to be written into the data line concerned. When the gray-scale voltage to be written is higher than a median gray-scale voltage, a high drive voltage is selected, and when the gray-scale voltage to be written is lower than the median gray-scale voltage, a low drive voltage is selected. However, if the median gray-scale voltage is greatly separated from a central value in a range of a drive voltage, the precharge voltage is determined in view of factors including higher place bit signals, so that it becomes near to the central value in the range of the drive voltage. Thus, when the analog buffer outputs the analog gray-scale voltage, the width pulled up by the analog buffer supplying an electric charge to the data line and the width pulled down by the analog buffer drawing an electric charge from the data line, can be made to about a half of a voltage difference between the high drive voltage and the low drive voltage, with the result that the time required for writing the analog gray-scale voltage to the data line can be shortened.
Here, under an ordinary practice, the drive voltage does not beyond the range of a power supply voltage. Therefore, the xe2x80x9chigh drive voltagexe2x80x9d and the xe2x80x9clow drive voltagexe2x80x9d as mentioned above ordinarily become a maximum value VDD and a minimum value VSS of the power supply voltage, respectively. However, the xe2x80x9chigh drive voltagexe2x80x9d may be slightly lower than the maximum value VDD of the power supply voltage, and the xe2x80x9clow drive voltagexe2x80x9d may be slightly higher than the minimum value VSS of the power supply voltage. In addition, the precharge voltage can be constituted of a plurality of voltages including the maximum value VDD and the minimum value VSS of the power supply voltage. In this case, the precharge voltage is selected on the basis of the digital signal of high place bits including the most significant bit.